This application is based upon and claims priority from prior French Patent Application No. 00-08576, filed Jul. 3, 2000, the entire disclosure of which is herein incorporated by reference.
1. Field of the Invention
The present invention relates to semiconductor device fabrication, and more specifically to the polishing of the surface of an integrated circuit wafer.
2. Description of Related Art
The present invention is directed to a method of determining the time for polishing the surface of an integrated circuit wafer, which includes a layer of a material to be polished, on a mechanical/chemical polishing machine. Conventionally, the polishing time for the surface of a wafer is determined through trial and error on successive wafers. This trial and error process causes the successive wafers that are used to make the polishing time determination to then be unusable, so they must consequently be rejected.
In view of these drawbacks, it is an object of the present invention to overcome the above-mentioned drawbacks and to provide a method for determining the time for polishing an integrated circuit wafer so as to remove from a layer to be polished a predetermined average thickness so as to confer on it a particular final topography.
One embodiment of the present invention provides a method of determining the time for polishing the surface of an integrated circuit wafer to be polished on a polishing machine so as to remove from a layer of a material to be polished a predetermined average thickness and confer a particular final topography. According to the method, a sample wafer is fabricated by depositing a layer of the material to be polished such that the layer forms at least one high plateau and at least one low plateau that are joined by a sudden transition. At least one initial profile of the layer that includes the transition on the surface of the sample wafer is topographically scanned, and the surface of the sample wafer is polished on the polishing machine at a particular polishing pressure for a particular polishing time. The final profile of the polished layer is topographically scanned in an area corresponding to the initial profile, and the initial topographical scan and the final topographical scan of the sample wafer are converted into Fourier series. The surface of the wafer to be polished is topographically scanned, and the topographical scan of the wafer to be polished is converted into a Fourier series. The time for polishing the wafer to be polished is calculated from the Fourier series and the average thickness to be removed. In a preferred embodiment, the wafer to be polished is polished for the calculated polishing time.
Other objects, features, and advantages of the present invention will become apparent from the following detailed description. It should be understood, however, that the detailed description and specific examples, while indicating preferred embodiments of the present invention, are given by way of illustration only and various modifications may naturally be performed without deviating from the present invention.